1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device. More specifically, the present invention relates to a non-volatile semiconductor memory device having a matrix-shaped memory cell area including a plurality of memory cells arranged in a plurality of rows and a plurality of columns.
2. Description of the Background Art
As one configuration of a non-volatile semiconductor memory device, VGA (virtual ground array) is known. The VGA configuration refers to a configuration in which adjacent memory cells share a diffusion layer. The area of the non-volatile semiconductor memory device can be reduced by adopting the VGA configuration. FIG. 17 shows a non-volatile semiconductor memory device having the VGA configuration. The non-volatile semiconductor memory device shown in FIG. 17 has the VGA configuration and has a hierarchical bit line structure including main bit lines and sub-bit lines.
The non-volatile semiconductor memory device shown in FIG. 17 is divided into three areas A to C. FIG. 17 shows main bit lines MOi, MEi, MOi+1, MEi+1, and sub-bit lines 91Ai to 94Ai, 91Ai+1 to 94Ai+1, 91Bi to 94Bi, 91Bi+1 to 94Bi+1 as the lines in the column direction (vertical direction). FIG. 17 also shows word lines AWLB, BWLB, and selection lines SEL1U to SEL4U, SEL1L to SEL4L as the lines in the row direction (horizontal direction). The word line AWLB is connected to the gates of memory cells AP to AV, and the word line BWLB is connected to the gates of memory cells BP to BV. Selection transistors, which are switches for controlling connection between the main bit lines and the sub-bit lines, are disposed between the main bit lines and the sub-bit lines, if necessary. The main bit lines and the sub-bit lines form a hierarchical structure with the main bit lines at the top and the sub-bit lines at the bottom.
The operation of the non-volatile semiconductor memory device shown in FIG. 17 that is configured as above will be described. As an example, the case where “a read on the source side” with respect to a memory cell BQ is performed will be described. A memory cell storing data “0” is referred to as “being in a program state”, and a memory cell storing data “1” is referred to as “being in an erase state”. In order to perform a read on the source side with respect to a memory cell, it is necessary to apply voltages of about 4.5 V, about 0 V (substantially ground voltage) and about 1 V to the gate, the source and the drain of the memory cell, respectively.
As shown in FIG. 17, the drain of the memory cell BQ is connected to the sub-bit line 92Bi, and the sub-bit line 92Bi is connected to the main bit line MEi via a selection transistor 95. The source of the memory cell BQ is connected to the sub-bit line 93Bi, and the sub-bit line 93Bi is connected to the main bit line MOi via a selection transistor 96. Therefore, in order to perform a read on the source side with respect to a memory cell BQ, a voltage of about 3 V is applied to the selection lines SEL2L, SEL1U to control the selection transistors 95, 96 to be ON, and voltages of about 1 V, about 0 V and about 4.5 V can be applied to the main bit lines MEi, MOi and the word line BWLB, respectively. Thus, voltages of about 4.5 V, about 0 V (substantially ground voltage) and about 1 V can be applied to the gate, the source and the drain of the memory cell BQ, respectively.
When a predetermined voltage is applied to each line in this manner and the data stored in the memory cell BQ is “0”, the threshold value of the gate voltage is high, so that almost no current flows from the main bit line MEi to the main bit line MOi. Consequently, the potential of the main bit line MOi is not substantially increased. On the other hand, when the data stored in the memory cell BQ is “1”, the threshold value of the gate voltage is low, so that a current flows from the main bit line MEi to the main bit line MOi. Consequently, the potential of the main bit line MOi is increased by a voltage corresponding to the current that has flown. Therefore, data can be read from the memory cell BQ by detecting the voltage of the main bit line MOi.
Whether the data read from the memory cell BQ is “0” or “1” can be determined in the following manner. A sense amplifier (not shown) amplifies and outputs a difference between a voltage of the main bit line MOi during a read operation and a predetermined voltage that serves as a reference (hereinafter, referred to as “reference voltage”). When the voltage of the main bit line MOi is higher than the reference voltage, it is determined that the read data is “1”. On the other hand, when the voltage of the main bit line MOi is lower than the reference voltage, it is determined that the read data is “0”.
A reference cell is used to generate the reference voltage as described above. The reference cell is designed to output the reference voltage when it is controlled to be ON. The reference cell is constituted by, for example, a MOS transistor. Such a reference cell is often disposed outside the memory cell area in the non-volatile semiconductor memory device as shown in FIG. 17.
Data read from one memory cell is output to the outside of the memory cell area via the main bit line and the sub-bit line connected to the memory cell. The main bit lines and the sub-bit lines used for reading data are associated with a parasitic capacitance in accordance with the lengths of the bit lines, whether or not there are other bit lines adjacent to the bit lines, or the number of connected memory cells or the like. This parasitic capacitance is a factor that may delay a data read operation. More specifically, when the parasitic capacitance is large, the delay amount during a data read becomes large, and when the parasitic capacitance is small, the delay amount during a data read becomes small.
As described above, the reference cell is often provided in a predetermined position outside the memory cell area. Therefore, unlike the memory cell, it is difficult to connect the reference cell to the main bit lines, which are connected to a plurality of memory cells and the sub-bit lines. Therefore, the line connected to the reference cell is not associated with a parasitic capacitance that is equal to the parasitic capacitance associated with the main bit line connected to the memory cell. Consequently, a phenomenon occurs in which, the parasitic capacitance generated on the side of the memory cell to be read as seen from the sense amplifier does not match the parasitic capacitance generated on the side of the reference cell (this phenomenon is referred to as “capacitance unbalance”). When such capacitance unbalance occurs, the delay amount when the voltage of the main bit line connected to the memory cell is output does not match the delay amount when the reference voltage is output from the reference cell.
Regarding this problem, a method for equalizing the parasitic capacitance associated with the bit line on the memory cell side as seen from the sense amplifier with the parasitic capacitance associated with the line on the reference cell side is known. The method will be described in detail with reference to FIG. 17 below.
As described above, when reading data from the memory cell BQ, the main bit lines MOi, MEi, and the sub-bit lines 92Bi, 93Bi are used. Therefore, when reading data from the memory cell BQ, a parasitic capacitance in accordance with the length of each of the bit lines is associated therewith. Then, the line with which a parasitic capacitance equal to the parasitic capacitance associated with each of the bit lines is associated can be connected to the reference cell. Thus, the parasitic capacitance associated with the bit line connected to the reference cell can be equal to the parasitic capacitance associated with the bit line connected to the memory cell BQ.
More specifically, the same voltage as the voltage applied to the main bit line and the sub-bit line used for a data read is applied to the main bit line and the sub-bit line that are not used for a data read, and these bit lines can be connected to the reference cell. For example, when reading data from the memory cell BQ, voltages of about 0 V and about 1 V are applied to the main bit lines MOi+1, MEi+1, respectively (thus, voltages of about 0 V and about 1 V are also applied to the sub-bit lines 93Bi+1, 92Bi+1, respectively), and the main bit lines MOi+1, MEi+1 can be connected to the reference cell. Thus, the bit line connected to the reference cell is associated with the same parasitic capacitance as that of the bit line connected to the memory cell BQ. Regarding the above-described technique, U.S. Pat. Nos. 5,963,465 and 6,351,415 (hereinafter, referred to as “Reference 1” and “Reference 2”) can be referred to.
However, the method for allowing the parasitic capacitance to be associated in the above-described manner has the following problem. Data is read from a memory cell connected to the same word line as the selected memory cell (e.g., memory cell BU in the case where the memory cell BQ is selected), and thus the non-volatile semiconductor memory device may malfunction.
In order to solve this problem, a non-volatile semiconductor memory device shown in FIG. 18 is known. FIG. 18 is a diagram showing the configuration of a non-volatile semiconductor memory device disclosed in U.S. Pat. No. 6,128,226 (hereinafter, referred to as “Reference 3”). The non-volatile semiconductor memory device shown in FIG. 18 will be described.
The non-volatile semiconductor memory device shown in FIG. 18 includes memory cells, bit lines BL, word lines WL, reference bit lines BLR, a Y decoder 1000, a reference unit 1002 and a sense amplifier 1004. The memory cells are arranged in a matrix. The bit lines BL are arranged in the column direction between the memory cells arranged in a matrix. The words lines WL are arranged in the row direction between the memory cells arranged in a matrix. The reference bit lines BLR are lines with which a parasitic capacitance equal to the parasitic capacitance associated with the bit lines BL is associated during a data read operation. The Y decoder 1000 connects the bit line BL to the sense amplifier 1004, the memory cell to be read being connected to the bit line BL. The reference unit 1002 generates a reference voltage Vref that serves as a reference. The sense amplifier 1004 amplifies and output a difference between the voltage Vcell of the bit line BL output from the Y decoder 1000 and the reference voltage Vref.
In the non-volatile semiconductor memory device shown in FIG. 18, a data read is performed in the following manner. First, when reading data from a certain memory cell, data is read out to the Y decoder 1000, using two bit lines BL connected to the diffusion layer of this memory cell and a word line WL connected to the gate of this memory cell. The Y decoder 1000 outputs the voltage Vcell of the bit line BL connected on the drain side to the sense amplifier 1004.
On the other hand, the reference unit 1002 generates the reference voltage Vref, and outputs it to the sense amplifier 1004. In this case, two reference bit lines BLR are selected, and connected to the reference unit 1002. Thus, the parasitic capacitance associated with the bit lines BL connected to the memory cell to be read can be equal to the parasitic capacitance associated with the reference lines BLR connected to the reference unit 1002. That is to say, the problem of capacitance unbalance can be solved. Consequently, the delay amount in reading from the memory cell can be equal to the delay amount in reading from the reference unit 1002.
Regarding the non-volatile semiconductor memory device, U.S. Pat. No. 6,272,043 (hereinafter, referred to as “Reference 4”) discloses a method for performing a read on the source side in a non-volatile semiconductor memory device as shown in FIG. 19. In the non-volatile semiconductor memory device shown in FIG. 19, a reference circuit 2045 includes a reference current source 2040 and a current/voltage converting circuit 2050, a memory arrangement 2015 includes a virtual ground array 2000 and a current/voltage converting circuit 2030. The current/voltage converting circuit 2050 is constituted by a resistance element and converts a current generated in the reference current source 2040 to a reference voltage 2055. The current/voltage converting circuit 2030 is constituted by a resistance element and converts a current output from a memory cell in the virtual ground array 2000 to a read voltage 2065. A comparing circuit 2060 is constituted by a differential amplifier and compares the reference voltage 2055 and the read voltage 2065. Thus, the state of the memory cell in the virtual ground array 2000 can be determined.
However, the non-volatile semiconductor memory device shown in FIG. 18 has a problem in that it is difficult to reduce the size of the circuit. More specifically, in the non-volatile semiconductor memory device shown in FIG. 18, extra reference bit lines BLR for generating a read delay in the reference cell are provided. Therefore, it is necessary to provide an area in which the reference bit lines BLR are provided in the non-volatile semiconductor memory device.